The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

May. 30, 2013
Applicant:

National Institute of Advanced Industrial Science and Technology, Tokyo, JP;

Inventors:

Shigeki Sakai, Tsukuba, JP;

Wei Zhang, Tsukuba, JP;

Mitsue Takahashi, Tsukuba, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 21/324 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 21/02197 (2013.01); H01L 21/02266 (2013.01); H01L 21/28194 (2013.01); H01L 21/28291 (2013.01); H01L 21/324 (2013.01); H01L 29/495 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09);
Abstract

Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body () and a gate electrode conductor () are sequentially laminated in this order on a semiconductor base () that has a source region () and a drain region (). The insulating body () is configured by laminating a first insulating body () and a second insulating body () in this order on the base (), and the second insulating body () is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.


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