The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2017
Filed:
May. 11, 2015
Applicant:
Wisconsin Alumni Research Foundation, Madison, WI (US);
Inventor:
Jing Li, Madison, WI (US);
Assignee:
Wisconsin Alumni Research Foundation, Madison, WI (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 7/10 (2006.01); G06F 13/40 (2006.01); G11C 5/02 (2006.01); G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 15/04 (2006.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01);
U.S. Cl.
CPC ...
G11C 7/10 (2013.01); G06F 13/4022 (2013.01); G11C 5/025 (2013.01); G11C 7/1006 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); G11C 11/005 (2013.01); G11C 13/0002 (2013.01); G11C 13/0021 (2013.01); G11C 15/046 (2013.01); G11C 2207/005 (2013.01); G11C 2213/77 (2013.01);
Abstract
A computer architecture employs multiple intercommunicating tiles each holding an array of memory elements. Programmable decoding circuitry allows these memory elements to be used as local memories (including content addressable memories or random access memories), logic elements or interconnect elements. The ability to dynamically change the function of any of these tiles allows tight integration of memory and logic tailored to particular calculation problems reducing costs in data transfer.