The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

Apr. 29, 2014
Applicant:

Diablo Technologies Inc., Ottawa, Ontario, CA;

Inventors:

Michael L. Takefman, Nepean, CA;

Maher Amer, Nepean, CA;

Riccardo Badalone, St. Lazare, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 12/08 (2016.01); G06F 12/10 (2016.01); G06F 12/0804 (2016.01); H03M 13/05 (2006.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0804 (2013.01); G06F 11/1008 (2013.01); G06F 12/1027 (2013.01); H03M 13/05 (2013.01);
Abstract

A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system provides a one-hot address cache comprising a plurality of one-hot addresses and a host interface to a host memory controller of a host system. Each one-hot address of the plurality of one-hot addresses has a bit width. The plurality of one-hot addresses is configured to store the data associated with a corresponding memory address in an address space of a memory system and provide the data to the host memory controller during a memory map learning process. The plurality of one-hot addresses comprises a zero address of the bit width and a plurality of non-zero addresses of the bit width, and each one-hot address of the plurality of non-zero addresses of the one-hot address cache has only one non-zero address bit of the bit width.


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