The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2017
Filed:
Aug. 30, 2016
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Chih-Jung Chen, Hsinchu County, TW;
Tzu-Ping Chen, Hsinchu County, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/792 (2006.01); H01L 31/119 (2006.01); H01L 27/11568 (2017.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/3213 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/28282 (2013.01); H01L 21/32133 (2013.01); H01L 29/4234 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract
The present invention provides a non-volatile memory structure, which includes a substrate, a gate dielectric layer disposed on the substrate, two charge trapping layers, disposed on two sides of the gate dielectric layer respectively and disposed on the substrate, a gate conductive layer disposed on the gate dielectric layer and on the charge trapping layers, wherein a sidewall of the gate conductive layer is aligned with a sidewall of one of the two charge trapping layers, and at least one vertical oxide layer, disposed beside the sidewall of the gate conductive layer.