The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Jan. 28, 2015
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Ravi Keshav Joshi, Villach, AT;

Juergen Steinbrenner, Noetsch, AT;

Christian Fachmann, Fuernitz, AT;

Petra Fischer, Wernberg, AT;

Roman Roth, Sattfendorf, AT;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/32134 (2013.01); H01L 21/76885 (2013.01); H01L 24/00 (2013.01); H01L 21/32139 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.


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