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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9773547 B1

PDFFull Text
Date of Patent:
Sep. 26, 2017

Filed:

Jan. 31, 2014

Non-volatile memory with multiple latency tiers

Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Richard H. Henze, San Carlos, CA (US);

Naveen Muralimanohar, Santa Clara, CA (US);

Yoocharn Jeon, Palo Alto, CA (US);

Martin Foltin, Fort Collins, CO (US);

Erik Ordentlich, San Jose, CA (US);

Gregg B. Lesartre, Fort Collins, CO (US);

R. Stanley Williams, Portola Valley, CA (US);

Assignee:

Hewlett Packard Enterprise Development LP, Houston, TX (US);

Attorney:

Fabian Vancott

Primary Examiner:

Hoai V Ho

Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01); G11C 5/02 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 5/025 (2013.01); G11C 11/005 (2013.01); G11C 13/0069 (2013.01); H01L 23/528 (2013.01); H01L 27/2463 (2013.01); H01L 27/2481 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/14 (2013.01); H01L 45/142 (2013.01); H01L 45/143 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0011 (2013.01); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01); G11C 2213/77 (2013.01); G11C 2213/79 (2013.01);
Abstract

A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.

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