The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Aug. 27, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventor:

Ya-Min Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01);
Abstract

A method and a system for creating a semiconductor device layout are disclosed. The system includes a display screen for displaying at least one graphic representation of a device layout; a memory storing a device library comprising a plurality of predefined target device layouts; and at least one processor coupled to the display screen and the memory and programmed to: prompt a user to draw at least one portion of at least one layer of a desired device layout to create a current device layout; identify at least one predefined target device layout from the device library that matches the at least one portion of the at least one layer; display the current device layout and the identified at least one predefined target device layout on the display screen; and indicate at least one difference between the current device layout and the at least one predefined target device layout on the display screen.


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