The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Apr. 16, 2015
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Fabrice Raymond Morlat, Montbard, FR;

Gerard Tarroux, Villeneuve-Loubet, FR;

Fabien Campana, Les Adrets de l'Esterel, FR;

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01);
Abstract

Methods and systems provide aspects of electronics layout design including copying of layout element(s) and graphically defining a one-to-one correspondence between two elements. An exemplary method may include defining a cloning constraint for a layout, rendering a user interface (UI) to display at least one of a schematic and form representation of the layout, and receiving a selection of at least one element in the layout. The method may create a movable drag set based on the selection, and responsive to a matching of at least one element of the drag set with another element in the layout, performing a one-to-one correspondence for the matched elements. The matching may be an overlap of at least one element in the drag set with an element in the layout having the same master.


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