Data synchronizer for latching an asynchronous data signal relative to a clock signal

Abstract

A data synchronizer that latches an asynchronous input data signal relative to a clock signal. The data synchronizer includes in input circuit, first and second pass gates, first and second inverters, and a gate controller. The input circuit drives first and second data nodes to opposite logic states based on the asynchronous input data signal. Each pass gate is coupled between an input data node and a capture node. The inverters are cross-coupled between the capture nodes. The gate controller is capable of keeping the pass gates at least partially open during a metastable condition of the capture nodes, and closes the pass gates when the capture nodes resolve to opposite logic states. The capture nodes may be buffered in a substantially balanced manner to provide a buffered output, and the buffered output may be registered into the clock domain. The data synchronizer may be implemented using FinFET devices.