The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Jul. 20, 2015
Applicant:

Ecole Polytechnique Federale DE Lausanne (Epfl), Lausanne, CH;

Inventors:

Cem Alper, Lausanne, CH;

Livio Lattanzio, Lausanne, CH;

Mihai Adrian Ionescu, Ecublens, CH;

Luca De Michielis, Lausanne, CH;

Nilay Dagtekin, Lausanne, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/93 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); B82Y 10/00 (2011.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/739 (2006.01); H01L 29/775 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78648 (2013.01); B82Y 10/00 (2013.01); H01L 29/0676 (2013.01); H01L 29/42356 (2013.01); H01L 29/66439 (2013.01); H01L 29/66977 (2013.01); H01L 29/7391 (2013.01); H01L 29/78696 (2013.01); H01L 29/775 (2013.01);
Abstract

The present invention concerns a semiconductor tunneling Field-Effect device including a source, a drain, at least one elongated semiconductor structure extending in an elongated direction, a first gate, and a second gate. The first gate has a length extending in said elongated direction and is positioned on a first side of the at least one elongated semiconductor structure, and the second gate has a length extending in said elongated direction and is positioned on a second opposing side of the at least one elongated semiconductor structure. The first and second gates extend along the first and second sides of the at least one elongated semiconductor structure to define an overlap zone sandwiched between the first gate and the second gate, said overlap zone extending the full length of the first and/or second gate along the at least one elongated semiconductor structure.


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