The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Nov. 25, 2015
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventor:

Guowei Zhang, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/0692 (2013.01); H01L 29/0847 (2013.01); H01L 29/66659 (2013.01); H01L 29/7835 (2013.01); H01L 29/665 (2013.01);
Abstract

High voltage devices and methods for forming thereof are disclosed. A high voltage device includes a substrate having a device region, where the device region includes a source region and a drain region defined thereon. A transistor is disposed on the device region. The transistor includes a gate disposed over the substrate and in between the source and drain regions. First and second device wells are disposed in the substrate within the device region. The first device well is adjacent to a second side of the gate and the second device well is adjacent to a first side of the gate. Isolation regions are disposed within the substrate. The isolation regions include a device isolation region surrounding the device region and one or more isolation fingers disposed in a first portion of the device region adjacent to the first side of the gate.


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