The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2017
Filed:
May. 31, 2016
Applicant:
United Microelectronics Corp., Hsinchu, TW;
Inventors:
Chun-Hsien Lin, Tainan, TW;
Min-Hsien Chen, Taichung, TW;
Assignee:
United Microelectronics Corp., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 21/285 (2006.01); H01L 29/51 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28088 (2013.01); H01L 21/2855 (2013.01); H01L 21/823842 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/66575 (2013.01); H01L 29/165 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66636 (2013.01);
Abstract
A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.