The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Feb. 09, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Carl Z. Zhou, Plano, TX (US);

Keith A. Remack, Richardson, TX (US);

John A. Rodriguez, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 11/221 (2013.01); G11C 29/028 (2013.01); G11C 29/50016 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 29/50 (2013.01);
Abstract

A method of setting the reference voltage for sensing data states in integrated circuits including ferroelectric random access memory (FRAM) cells of the one-transistor-one capacitor (1T-1C) type. In an electrical test operation, some or all of the FRAM cells are programmed to a particular polarization state. A 'shmoo' of the reference voltage for sensing the data state is performed, at one or more worst case electrical or environmental conditions for that data state, to determine a reference voltage limit at which the weakest cell fails to return the correct data when read. A configuration register is then written with a reference voltage based on this reference voltage limit, for example at the limit plus/minus a tolerance.


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