The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Sep. 02, 2013
Applicant:

Virident Systems, Llc, San Jose, CA (US);

Inventors:

Kenneth Alan Okin, Saratoga, CA (US);

George Moussa, Dublin, CA (US);

Kumar Ganapathy, Los Altos, CA (US);

Vijay Karamcheti, Los Altos, CA (US);

Rajesh Parekh, Los Altos, CA (US);

Assignee:

Virident Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G06F 13/16 (2006.01); G11C 5/04 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1072 (2013.01); G06F 13/1694 (2013.01); G11C 5/04 (2013.01);
Abstract

A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.


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