The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2017
Filed:
Sep. 24, 2013
Intel Corporation, Santa Clara, CA (US);
Siddhartha Chhabra, Hillsboro, OR (US);
Uday R. Savagaonkar, Portland, OR (US);
Michael A. Goldsmith, Lake Oswego, OR (US);
Simon P. Johnson, Beaverton, OR (US);
Rebekah M. Leslie-Hurd, Portland, OR (US);
Francis X. McKeen, Portland, OR (US);
Gilbert Neiger, Portland, OR (US);
Raghunandan Makaram, Northborough, MA (US);
Carlos V. Rozas, Portland, OR (US);
Amy L. Santoni, Scottsdale, AZ (US);
Vincent R. Scarlata, Beaverton, OR (US);
Vedvyas Shanbhogue, Austin, TX (US);
Wesley H. Smith, Raleigh, NC (US);
Ittai Anati, Haifa, IL;
Ilya Alexandrovich, Haifa, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section that is convertible in response to a section conversion instruction.