The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Aug. 10, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Xin Guo, San Jose, CA (US);

Feng Zhu, San Jose, CA (US);

Eric L. Hoffman, Lafayette, CO (US);

Jing-Jing Li, Santa Clara, CA (US);

David J. Pelster, Longmont, CO (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 12/10 (2016.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0608 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01); G06F 12/10 (2013.01); G11C 29/76 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/152 (2013.01); G06F 2212/202 (2013.01); G06F 2212/253 (2013.01); G06F 2212/657 (2013.01);
Abstract

Provided are a method and apparatus for remapping logical to physical addresses for a non-volatile memory having dies. Bands extend through the dies and planes in the dies extending through the bands define addressable blocks. A first remapping of a logical-to-physical mapping is performed by remapping logical addresses of blocks in a first end of the bands that map to defective physical blocks to map to good physical blocks at a second end of the bands. After performing the first remapping, a second remapping of the logical-to-physical mapping is performed by remapping logical addresses in the second end of bands that map to defective blocks to map to good physical blocks in the first end of bands.


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