The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2017
Filed:
Jul. 04, 2014
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Chia-Fu Hsu, Tainan, TW;
Chun-Mao Chiou, Chiayi County, TW;
Shih-Chieh Hsu, New Taipei, TW;
Lung-En Kuo, Tainan, TW;
You-Di Jhang, New Taipei, TW;
Jian-Cun Ke, Tainan, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 29/513 (2013.01); H01L 29/6656 (2013.01); H01L 29/7833 (2013.01); H01L 29/4966 (2013.01);
Abstract
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a stack structure on the interfacial layer; patterning the stack structure to form a gate structure on the interfacial layer; forming a liner on the interfacial layer and the gate structure; and removing part of the liner and part of the interfacial layer for forming a spacer.