The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Sep. 16, 2016
Applicant:

Deca Technologies Inc., Tempe, AZ (US);

Inventor:

Christopher M. Scanlan, Chandler, AZ (US);

Assignee:

DECA Technologies Inc., Tempe, AZ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 21/48 (2006.01); H01L 25/065 (2006.01); H01L 23/367 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/4853 (2013.01); H01L 21/4882 (2013.01); H01L 21/561 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/3675 (2013.01); H01L 24/09 (2013.01); H01L 25/0655 (2013.01); H01L 2221/68354 (2013.01); H01L 2221/68359 (2013.01); H01L 2924/15174 (2013.01);
Abstract

A method of making a semiconductor device can include providing a temporary carrier with adhesive. A first semiconductor die and a second semiconductor die can be mounted face up to the temporary carrier such that back surfaces of the first semiconductor die and the second semiconductor die are depressed within the adhesive. An embedded die panel can be formed by encapsulating at least four sides surfaces and an active surface of the first semiconductor die, the second semiconductor die, and side surfaces of the conductive interconnects in a single step. The conductive interconnects of the first semiconductor die and the second semiconductor die can be interconnected without a silicon interposer by forming a fine-pitch build-up interconnect structure over the embedded die panel to form at least one molded core unit. The at least one molded core unit can be mounted to an organic multi-layer substrate.


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