The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2017
Filed:
Mar. 18, 2015
Applicant:
Globalfoundries Singapore Pte. Ltd., Singapore, SG;
Inventors:
Ranjan Rajoo, Singapore, SG;
Kai Chong Chan, Singapore, SG;
Assignee:
GLOBALFOUNDRIES SINGAPORE PTE. LTD., Singapore, SG;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/304 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/304 (2013.01); H01L 21/76898 (2013.01); H01L 25/50 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06555 (2013.01);
Abstract
Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces. The wafer includes edge and non-edge regions. The wafer includes a plurality of devices and partially processed TSV contacts disposed in the non-edge region and a groove disposed at the edge region. The groove enables edges of the wafer to be automatically trimmed off as the wafer is subject to a back-grinding planarization process to expose the TSV contacts in the non-edge region of the wafer.