The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Apr. 30, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Kuo-Chung Yee, Taoyuan, TW;

Chun Hui Yu, Zhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 23/49894 (2013.01); H01L 24/10 (2013.01); H01L 24/81 (2013.01); H01L 24/97 (2013.01); H01L 2224/10 (2013.01); H01L 2224/16 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/81 (2013.01); H01L 2224/97 (2013.01); H01L 2924/157 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15788 (2013.01); H01L 2924/181 (2013.01); H01L 2924/351 (2013.01);
Abstract

A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.


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