The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Jun. 05, 2014
Applicant:

Cirrus Logic, Inc., Austin, TX (US);

Inventors:

Zhonghai Shi, Austin, TX (US);

Vince Deems, Austin, TX (US);

Hong Tian, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/3205 (2006.01); H01L 21/762 (2006.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01); H01L 21/763 (2006.01);
U.S. Cl.
CPC ...
H01L 21/32055 (2013.01); H01L 21/763 (2013.01); H01L 21/76224 (2013.01); H01L 27/0802 (2013.01); H01L 28/20 (2013.01); H01L 29/0649 (2013.01);
Abstract

In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion.


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