The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2017
Filed:
Jan. 12, 2016
Eun-jung Kim, Daegu, KR;
Sung-un Kwon, Suwon-si, KR;
Yong-kwan Kim, Yongin-si, KR;
Yoo-sang Hwang, Suwon-si, KR;
Young-sik Seo, Hwaseong-si, KR;
Eun-Jung Kim, Daegu, KR;
Sung-Un Kwon, Suwon-si, KR;
Yong-Kwan Kim, Yongin-si, KR;
Yoo-Sang Hwang, Suwon-si, KR;
Young-Sik Seo, Hwaseong-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
In a method of manufacturing a semiconductor device, sacrificial layer patterns extending in a first direction are formed on an etch target layer. Preliminary mask patterns are formed on opposite sidewall surfaces of each of the sacrificial layer patterns. A filling layer is formed to fill a space between the preliminary mask patterns. Upper portions of the preliminary mask patterns are etched to form a plurality of mask patterns. Each of the mask patterns is symmetric with respect to a plane passing a center point of each of the mask patterns in a second direction substantially perpendicular to the first direction and extending in the first direction. The sacrificial layer patterns and the filling layer are removed. The etch target layer is etched using the mask patterns as an etching mask to form a plurality of target layer patterns.