The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Nov. 01, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Mosaddiq Saifuddin, San Diego, CA (US);

SankaraRao Kunapareddy, San Diego, CA (US);

Keunsoo Roh, San Diego, CA (US);

Chun Xiang He, San Diego, CA (US);

Pratik Patel, San Diego, CA (US);

Nicholas Ambur, San Diego, CA (US);

Jeremy Haugen, Vista, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 11/406 (2006.01); G11C 7/10 (2006.01); G11C 11/408 (2006.01); G06F 13/16 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40615 (2013.01); G06F 1/3225 (2013.01); G06F 1/3275 (2013.01); G06F 13/1636 (2013.01); G11C 7/1072 (2013.01); G11C 11/4087 (2013.01); G11C 11/40611 (2013.01); G11C 11/40618 (2013.01); G11C 11/40622 (2013.01);
Abstract

In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.


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