The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2017
Filed:
Dec. 23, 2014
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Federico Ardanaz, Hillsboro, OR (US);
Jonathan M. Eastep, Portland, OR (US);
Richard J. Greco, West Linn, OR (US);
Ramkumar Nagappan, Chandler, AZ (US);
Alan B. Kyker, Winters, CA (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/325 (2013.01); G06F 1/3287 (2013.01); G06F 1/3293 (2013.01);
Abstract
Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.