The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Mar. 05, 2014
Applicant:

At&s Austria Technologie & Systemtechnik Aktiengesellschaft, Leoben, AT;

Inventors:

Alexander Kasper, Graz, AT;

Dietmar Drofenik, Spielberg, AT;

Ravi Hanyal Shivarudrappa, Leoben, AT;

Michael Gössler, Kobenz, AT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01); H05K 1/02 (2006.01); H05K 3/46 (2006.01); H05K 1/09 (2006.01); H05K 1/11 (2006.01); H05K 1/16 (2006.01); H05K 3/00 (2006.01); H05K 3/10 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0298 (2013.01); H05K 1/028 (2013.01); H05K 1/09 (2013.01); H05K 1/115 (2013.01); H05K 1/162 (2013.01); H05K 3/0047 (2013.01); H05K 3/10 (2013.01); H05K 3/429 (2013.01); H05K 3/4611 (2013.01); H05K 3/4682 (2013.01); H05K 3/4691 (2013.01); H05K 3/4694 (2013.01); H05K 2201/0355 (2013.01); H05K 2201/096 (2013.01); H05K 2203/061 (2013.01); H05K 2203/063 (2013.01);
Abstract

A method for producing a printed circuit board () with multilayer subareas in sections, characterized by the following steps: a) providing at least one conducting foil (') and application of a dielectric insulating foil (′) to at least one subarea of the conducting foil; b) applying a structure of conducting paths (′) to the insulating layer (′); c) providing one further printed circuit board structure; d) joining of the further printed circuit board structure with the conducting foil (′) plus insulating layer (′) and conducting paths (′) by interposing a prepreg layer (′), and e) laminating the parts joined in step d) under pressing pressure and heat; and a printed circuit board produced according to this method.


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