The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Aug. 23, 2013
Applicant:

University of Calcutta, Kolkata, IN;

Inventor:

Abhijit Mallik, Sonarpur, IN;

Assignee:

UNIVERSITY OF CALCUTTA, Kolkata, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66977 (2013.01); H01L 29/0657 (2013.01); H01L 29/0843 (2013.01); H01L 29/1025 (2013.01); H01L 29/66356 (2013.01); H01L 29/66742 (2013.01); H01L 29/7391 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

Technologies are generally described herein generally relate to tunnel field-effect transistor (TFETs) structures with a gate-on-germanium source (GoGeS) on bulk silicon substrate for sub 0.5V (V) operations. In some examples, the GoGeS structure may include an increase in tunneling area and, thereby, a corresponding increases in the ON-state current I. In order to achieve supersteep sub-threshold swing, both the lateral tunneling due to gate electric-field and the non-uniform tunneling at the gate-edge due to field-induced barrier lowering (FIBL) may be suppressed through selection of component dimension in the device structure. Example devices may be fabricated using CMOS fabrication technologies with the addition of selective etching in the process flow.


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