The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Feb. 25, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Juergen Faul, Radebeul, DE;

Frank Jakubowski, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11568 (2017.01); H01L 21/762 (2006.01); H01L 21/28 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/3065 (2006.01); H01L 21/265 (2006.01); H01L 27/11521 (2017.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/26513 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76283 (2013.01); H01L 27/11521 (2013.01); H01L 27/1207 (2013.01); H01L 29/42336 (2013.01); H01L 29/42352 (2013.01);
Abstract

The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.


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