The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Oct. 14, 2013
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Minghui Han, San Jose, CA (US);

Amir Amirkhany, Sunnyvale, CA (US);

Ravindranath Kollipara, Palo Alto, CA (US);

Ralf Michael Schmitt, Mountain View, CA (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/28 (2006.01); G06F 3/06 (2006.01); G11C 5/04 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 3/0611 (2013.01); G06F 3/0635 (2013.01); G06F 3/0683 (2013.01); G11C 5/04 (2013.01); G11C 5/063 (2013.01); G11C 7/1084 (2013.01);
Abstract

A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.


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