The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Nov. 09, 2015
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Marco Giovanni Fontana, Milan, IT;

Massimo Montanaro, Cava Manara, IT;

Anthony R. Cabrera, Folsom, CA (US);

Gerald A. Kreifels, El Dorado Hills, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/064 (2013.01); G06F 3/0649 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 12/0253 (2013.01); G06F 2212/7211 (2013.01);
Abstract

Methods of wear leveling in a memory, and memories configured to perform such methods, are useful in extending cycling endurance in memories. Such methods include transferring data from a first block of the memory to a second block of the memory, erasing the first block, transferring data from a third block of the memory to the first block, erasing the third block, transferring data from the second block to the third block, swapping logical addresses for the first block and the third block with each other, and erasing the second block. Transferring data from the third block to the first block excludes a sub-sector of the third block that is to be erased.


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