The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Oct. 08, 2015
Applicant:

Ibiden Co., Ltd., Ogaki, JP;

Inventors:

Mitsuhiro Tomikawa, Ogaki, JP;

Kota Noda, Ogaki, JP;

Nobuhisa Kuroda, Ogaki, JP;

Haruhiko Morita, Ogaki, JP;

Assignee:

IBIDEN CO., LTD., Ogaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01); H05K 3/46 (2006.01); H05K 1/18 (2006.01); H05K 1/14 (2006.01); H05K 3/00 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4697 (2013.01); H05K 1/185 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16265 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01); H05K 1/141 (2013.01); H05K 3/0038 (2013.01); H05K 3/427 (2013.01); H05K 3/4602 (2013.01); H05K 3/4644 (2013.01); H05K 2201/10015 (2013.01); H05K 2203/1476 (2013.01);
Abstract

A wiring board with a built-in electronic component includes a substrate having cavity, an insulating layer formed on the substrate such that the insulating layer is covering the cavity, a conductor layer formed on the insulating layer, and an electronic component accommodated in the cavity and including a rectangular cuboid body and terminal electrodes such that each electrode has a metal film form formed on outer surface of the body, and via conductors formed in the insulating layer such that the via conductors are connecting the conductor layer and electrodes. The electrodes are arrayed in a matrix having rows and columns such that adjacent electrodes in row and column directions have the opposite polarities, and the conductor layer includes a line pattern shunting first group of the electrodes in one polarity and a solid pattern shunting second group of the electrodes in the other polarity.


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