The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Nov. 14, 2016
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventor:

David Cyrille Babin, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 5/02 (2006.01); H03M 5/20 (2006.01); G06F 1/32 (2006.01); G06F 13/40 (2006.01); G06F 9/44 (2006.01);
U.S. Cl.
CPC ...
H03M 5/20 (2013.01); G06F 1/3287 (2013.01); G06F 9/4401 (2013.01); G06F 13/4022 (2013.01);
Abstract

Embodiments are provided for a quaternary decoder that includes a plurality of decoder circuits, each decoder circuit coupled to a respective input line of a plurality of quaternary interface lines and to a respective pair of binary output lines; and a control logic circuit having a plurality of control signal lines coupled to each of the plurality of decoder circuits, the control logic circuit configured to: output a first sequence of logic levels, and output a second sequence of logic levels after the first sequence is complete; wherein at a time after the second sequence is complete, each decoder circuit is configured to output a pair of binary data values that correspond to a quaternary state of the respective input line, the quaternary state being one of four quaternary states including a logic high state, a logic low state, a floating state, and a tie-back state.


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