The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Sep. 03, 2015
Applicant:

Hypres Inc., Elmsford, NY (US);

Inventors:

Sergey K. Tolpygo, Putnam Valley, NY (US);

Denis Amparo, White Plains, NY (US);

Richard Hunt, Park Ridge, NJ (US);

John Vivalda, Poughkeepsie, NY (US);

Daniel Yohannes, Stamford, CT (US);

Assignee:

Hypres, Inc., Elmsford, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 39/24 (2006.01); H01L 39/02 (2006.01); H01L 39/22 (2006.01);
U.S. Cl.
CPC ...
H01L 39/2493 (2013.01); H01L 39/025 (2013.01); H01L 39/223 (2013.01);
Abstract

Superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit, which must cross each other both with and without contacts. All wiring lines and contacts must be fully superconducting, and in the prior art each wiring layer comprises a single metallic thin film. An alternative wiring layer is disclosed that comprises sequential layers of two or more different metals. Such a multi-metallic wiring layer may offer improved resistance to impurity diffusion, better surface passivation, and/or reduction of stress, beyond that which is attainable with a single-metallic wiring layer. The resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of Josephson junctions. Several preferred embodiments are disclosed, for both planarized and non-planarized processes. These preferred and other methods may be applied to digital circuits based on Rapid Single Flux Quantum logic, and to quantum computing using Josephson junction qubits.


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