The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Apr. 16, 2012
Applicants:

Patrice M. Parris, Phoenix, AZ (US);

Weize Chen, Phoenix, AZ (US);

Inventors:

Patrice M. Parris, Phoenix, AZ (US);

Weize Chen, Phoenix, AZ (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/823418 (2013.01); H01L 27/088 (2013.01); H01L 29/063 (2013.01); H01L 29/0634 (2013.01); H01L 29/66659 (2013.01); H01L 29/7835 (2013.01); H01L 29/0653 (2013.01); H01L 29/402 (2013.01);
Abstract

An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic.


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