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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9741731 B1

PDFFull Text
Date of Patent:
Aug. 22, 2017

Filed:

Dec. 22, 2014

Three dimensional stacked semiconductor structure

Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Erh-Kun Lai, Taichung, TW;

Yen-Hao Shih, New Taipei, TW;

Assignee:

MACRONIX INTERNATIONAL CO., LTD., Hsinchu, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Shouxiang Hu

Int. Cl.
CPC ...
H01L 27/11578 (2017.01); H01L 27/11524 (2017.01); H01L 27/24 (2006.01); H01L 27/108 (2006.01); H01L 27/11551 (2017.01); H01L 27/11529 (2017.01); H01L 27/06 (2006.01); H01L 27/02 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11578 (2013.01); H01L 27/0207 (2013.01); H01L 27/0688 (2013.01); H01L 27/10802 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11551 (2013.01); H01L 27/11565 (2013.01); H01L 27/249 (2013.01); H01L 27/2481 (2013.01); H01L 29/785 (2013.01); H01L 29/7841 (2013.01); H01L 29/792 (2013.01);
Abstract

A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a dielectric layer formed on the stacks, a plurality of conductive plugs independently formed in the dielectric layer; and a metal-oxide-semiconductor (MOS) layer formed on the dielectric layer. One of the stacks at least comprises a plurality of multi-layered pillars, and each of the multi-layered pillars comprises a plurality of insulating layers and a plurality of semiconductor layers arranged alternately. The MOS layer comprises a plurality of MOS structures connected to the conductive plugs respectively, and function as layer-selectors for selecting and decoding the to-be-operated layer.

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