The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Jun. 15, 2015
Applicant:

Globalfoundries Inc., Grand Caymay, KY;

Inventors:

Qiang Fang, Ballston Lake, NY (US);

Zhiguo Sun, Halfmoon, NY (US);

Jiehui Shu, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); H01L 21/31144 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01);
Abstract

A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric material with metal-filled via(s) situated therein, a protective layer over the bottom layer, and a top layer of dielectric material over the protective layer. A sacrificial layer of amorphous silicon is formed over the top layer of dielectric material, a protective layer is formed over the sacrificial layer and via(s) through each layer above the metal-filled via(s) to expose the metal of the metal-filled via(s). The protective layer is then selectively removed, as well as the sacrificial layer of amorphous silicon.


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