The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Jul. 29, 2016
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Matteo Dainese, Villach, AT;

Fabio Brucchi, Villach, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/336 (2006.01); H01L 21/225 (2006.01); H01L 29/06 (2006.01); H01L 29/739 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/761 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2257 (2013.01); H01L 21/2255 (2013.01); H01L 21/2256 (2013.01); H01L 21/761 (2013.01); H01L 21/76205 (2013.01); H01L 21/76224 (2013.01); H01L 21/76237 (2013.01); H01L 29/0619 (2013.01); H01L 29/6634 (2013.01); H01L 29/7395 (2013.01);
Abstract

A method of manufacturing a reverse-blocking IGBT (insulated gate bipolar transistor) includes forming a plurality of IGBT cells in a device region of a semiconductor substrate, forming a reverse-blocking edge termination structure in a periphery region of the semiconductor substrate which surrounds the device region, etching one or more trenches in the periphery region between the reverse-blocking edge termination structure and a kerf region of the semiconductor substrate, depositing a p-type dopant source which at least partly fills the one or more trenches and diffusing p-type dopants from the p-type dopant source into semiconductor material surrounding the one or more trenches, so as to form a continuous p-type doped region in the periphery region which extends from a top surface of the semiconductor substrate to a bottom surface of the semiconductor substrate after thinning of the semiconductor substrate at the bottom surface.


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