The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Dec. 23, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Samantika Sury, Westford, MA (US);

Simon Steely, Jr., Hudson, NH (US);

William Hasenplaugh, Boston, MA (US);

Joel Emer, Acton, MA (US);

David Webb, Groton, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0831 (2016.01); G06F 12/0817 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0833 (2013.01); G06F 12/0822 (2013.01); G06F 2212/283 (2013.01); Y02B 60/1225 (2013.01);
Abstract

Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache line, a second set of processor cores that each include a cache to store a copy of the cache line, and cache coherence logic to aggregate in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores and send a consolidated acknowledgment message to the first processor core.


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