The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2017
Filed:
Dec. 08, 2015
Freescale Semiconductor, Inc., Austin, TX (US);
Kevin Yi Cheng Chang, Tempe, AZ (US);
Muhammad Z. Islam, Chandler, AZ (US);
NXP USA, INC., Austin, TX (US);
Abstract
A low power clock distribution circuit system () includes a clock generator () for generating a high frequency clock signal that is supplied to a clock interconnect running to multiple lanes of an integrated circuit, each lane including a passive clock repeater circuit (e.g.,) having a differential-mode RLC network (e.g.,) that is shielded by an active guard ring structure (e.g.,) and that is coupled to receive first and second input clock signals (Vip, Vin) to provide clock signal gain boosting at a predetermined frequency range and clock signal attenuation out of the operating frequency range, thereby generating the first and second output clock signals (Vop, Von) that are provided to a clocked circuit (e.g.,).