The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Mar. 10, 2016
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Chun-Ming Chiou, Taoyuan, TW;

Yu-Jui Chang, Hsinchu, TW;

Cheng-Chi Lin, Yilan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/866 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/866 (2013.01); H01L 29/0607 (2013.01); H01L 29/0649 (2013.01); H01L 29/0684 (2013.01); H01L 29/66106 (2013.01);
Abstract

A semiconductor device includes a substrate; a well region of a first-conductivity-type, disposed in the substrate; a first impurity region of a first-conductivity-type disposed in the well region; a second impurity region of the second-conductivity-type disposed in the well region, the second-conductivity-type being opposite to the first-conductivity-type; a third impurity region disposed in the well region, a portion of the first impurity region overlapping a first portion of the third impurity region, a portion of the second impurity region overlapping a second portion of the third impurity region, and a third portion of the third impurity region being disposed between the first impurity region and the second impurity region; and a fourth impurity region and a barrier layer disposed in the substrate, the fourth impurity region and the barrier layer enclosing the well region from around and below, respectively.


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