The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Jan. 14, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Jan Hoentschel, Dresden, DE;

Peter Baars, Dresden, DE;

Hans-Peter Moll, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 27/12 (2006.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H01L 21/84 (2006.01); H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 27/06 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/26513 (2013.01); H01L 21/28518 (2013.01); H01L 21/76264 (2013.01); H01L 21/84 (2013.01); H01L 27/0629 (2013.01); H01L 27/1087 (2013.01); H01L 27/10829 (2013.01); H01L 28/60 (2013.01); H01L 29/0649 (2013.01); H01L 29/786 (2013.01); H01L 29/94 (2013.01); H01L 27/1085 (2013.01);
Abstract

A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an SOI wafer comprising a substrate, a buried oxide (BOX) layer formed over the substrate and a semiconductor layer formed over the BOX layer, removing the semiconductor layer in a first region of the wafer to expose the BOX layer, forming a dielectric layer over the exposed BOX layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin BOX layer of the wafer and a high-k dielectric layer formed on the ultra-thin BOX layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer.


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