The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Mar. 09, 2009
Applicants:

Paul Silvestri, Meridian, ID (US);

Jonathon G. Greenwood, Boise, ID (US);

Inventors:

Paul Silvestri, Meridian, ID (US);

Jonathon G. Greenwood, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 25/065 (2006.01); H01L 23/14 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/142 (2013.01); H01L 25/0657 (2013.01); H01L 23/13 (2013.01); H01L 23/3128 (2013.01); H01L 2224/4824 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06575 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/15311 (2013.01);
Abstract

Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the configuration includes a substrate with a recess, a first die carried by the substrate wherein the die substantially covers the recess, and a logic component carried by the die in a location exposed by the recess. The logic component can be substantially coplanar with the substrate. The die is electrically connected to a terminal on a one side of the substrate, and the logic component is electrically connected to a terminal on an opposite side of the substrate.


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