The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Oct. 31, 2016
Applicant:

Qi Ding Technology Qinhuangdao Co., Ltd., Qinhuangdao, CN;

Inventor:

Yi-Ho Chen, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49866 (2013.01); H01L 23/49894 (2013.01); H01L 24/81 (2013.01); H01L 2224/81192 (2013.01);
Abstract

A package substrate includes a first conductive wire layer having a first end portion and a second end portion opposite to the first end portion. A width of the first end portion is greater than that of the second end portion. An isolating layer covers the second end portion and contains the first conductive wire layer. The isolating layer defines blind holes which have conductive portions. A second conductive wire layer covers the isolating layer, and includes a third end portion facing the second end portion and a fourth end portion opposite to the third end portion. A width of the third end portion is greater than that of the fourth end portion. Solder mask layers are formed on the first conductive wire layer and on the second conductive wire layer, each solder mask layer defining an opening.


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