The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Mar. 09, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Won Seok Jung, Anyang-si, KR;

Joon Hee Lee, Seongnam-si, KR;

Keon Soo Kim, Suwon-si, KR;

Sun Yeong Lee, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/28 (2006.01); H01L 27/11573 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11575 (2017.01); H01L 27/11582 (2017.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28008 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.


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