The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2017
Filed:
Jun. 28, 2013
Intel Corporation, Santa Clara, CA (US);
Dannie G. Feekes, Newmarket-on-Fergus, IE;
Shlomo Raikin, Ofer, IL;
Blaise Fanning, Folsom, CA (US);
Joydeep Ray, Folsom, CA (US);
Julius Mandelblat, Haifa, IL;
Ariel Berkovits, Yuvalim, IL;
Eran Shifer, Tel Aviv, IL;
Zvika Greenfield, Kfar Sava, IL;
Evgeny Bolotin, Haifa, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.