The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

Oct. 23, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Alain Artieri, San Diego, CA (US);

Subbarao Palacharla, San Diego, CA (US);

Laurent Moll, San Jose, CA (US);

Raghu Sankuratri, San Diego, CA (US);

Kedar Bhole, San Diego, CA (US);

Vinod Chamarty, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/084 (2016.01); G06F 12/0895 (2016.01); G06F 12/0842 (2016.01); G06F 12/0846 (2016.01); G06F 12/127 (2016.01); G06F 12/0864 (2016.01); G06F 12/123 (2016.01);
U.S. Cl.
CPC ...
G06F 12/084 (2013.01); G06F 12/0842 (2013.01); G06F 12/0846 (2013.01); G06F 12/0895 (2013.01); G06F 12/127 (2013.01); G06F 12/0864 (2013.01); G06F 12/123 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/1048 (2013.01); G06F 2212/601 (2013.01); G06F 2212/62 (2013.01);
Abstract

A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.


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