The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

May. 05, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Anthony K. Stamper, Burlington, VT (US);

Edward C. Cooney, III, Jericho, VT (US);

Laurie M. Krywanczyk, Essex Junction, VT (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 23/528 (2006.01); H01L 23/58 (2006.01); H01L 21/768 (2006.01); H01L 21/268 (2006.01); H01L 21/3105 (2006.01); H01L 21/304 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/268 (2013.01); H01L 21/304 (2013.01); H01L 21/31051 (2013.01); H01L 21/768 (2013.01); H01L 23/528 (2013.01); H01L 23/585 (2013.01); H01L 23/5329 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 2223/54406 (2013.01); H01L 2223/54433 (2013.01);
Abstract

Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.


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