The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Dec. 31, 2013
Applicant:

Csmc Technologies Fab1 Co., Ltd., Jiangsu, CN;

Inventors:

Anna Zhang, Jiangsu, CN;

Xiaoming Li, Jiangsu, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3065 (2006.01); H01L 21/66 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 22/26 (2013.01); H01L 21/3065 (2013.01); H01L 21/6831 (2013.01);
Abstract

A method for wafer etching in a deep silicon trench etching process includes the following steps: a. electrostatically absorbing a wafer using an electrostatic chuck, and stabilizing the atmosphere required by the process (S); b. performing the sub-steps of a main process for the wafer, and the time for the sub-steps of the main process being shorter than the time required by the wafer main process; c. releasing the electrostatic adsorption of the electrostatic chuck on the wafer; d. determining whether the cumulative time of the sub-steps of the main process reaches a predetermined threshold or not, if so, performing the step e (S), and if not, repeating the operations in the steps a to c (S); and e. ending a wafer manufacturing process. The etching method avoids the wafer from continuous contact with the electrostatic chuck, reduces electrostatic accumulation on the surface of the wafer, and therefore solves the problem of resist reticulation on the surface of the wafer in the DSIE process.


Find Patent Forward Citations

Zhang, Anna. (2017). Method for wafer etching in deep silicon trench etching process (U.S. Patent No. 9728472). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9728472

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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