Sense circuit for rram

Abstract

A resistive random-access memory device includes a RRAM array including a plurality of RRAM cells coupled to a source line, a controller, a bit-line decoder, and a sense circuit. Each of the RRAM cells storing a logic state and is selected by the corresponding bit line and word line. The controller selects a selected RRAM cell by a bit-line signal and a selected word line and determines the logic state according to a sense signal. The bit-line decoder couples a data bit line to the selected bit line according to a bit-line signal. The sense circuit is coupled to the data bit line and compares a memory current flowing through the selected RRAM with a reference current to generate the sense signal. The sense circuit sinks the memory current from the data bit line when operating in a reset operation and a reverse read operation.