The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

May. 27, 2016
Applicant:

Stmicroelectronics International N.v., Amsterdam, NL;

Inventor:

Amit Chhabra, Delhi, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G05F 1/46 (2006.01); H03K 3/037 (2006.01); H03K 5/08 (2006.01); H03K 17/22 (2006.01);
U.S. Cl.
CPC ...
G11C 5/148 (2013.01); G05F 1/46 (2013.01); G05F 1/465 (2013.01); H03K 3/0377 (2013.01); H03K 5/082 (2013.01); H03K 17/223 (2013.01);
Abstract

When powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in the dual-rail memory circuit precisely controls an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.


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