The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Dec. 20, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Aarul Jain, New Delhi, IN;

Dirk Wendel, Grasbrunn, DE;

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/16 (2006.01); G06F 11/08 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 11/079 (2013.01); G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G06F 11/08 (2013.01); G06F 11/1016 (2013.01); G06F 11/167 (2013.01);
Abstract

An error detection system detects errors in data packets stored in a memory. A read signature generation circuit generates a read signature of a first data packet. A write signature generation circuit generates a write signature of a second data packet. When a trigger generation circuit generates a trigger signal, a first latching circuit stores a write address as a latch write address and a second latch stores the write signature as a latch write signature. A first synchronization and comparison circuit generates a comparison signal based on the latched write address and a read address. A second synchronization and comparison circuit generates a fault signal based on the comparison signal, the latched write signature, and the read signature.


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